1. Introduction to the R10000 Processor

1.3 What is an R10000 Microprocessor?

The R10000 processor uses the MIPS ANDES architecture, or Architecture with Non-sequential Dynamic Execution Scheduling.

The R10000 processor has the following major features (terms in bold are defined in the Glossary):

• it implements the 64-bit MIPS IV instruction set architecture (ISA)
• it can decode four instructions each pipeline cycle, appending them to one of three instruction queues
• it has five execution pipelines connected to separate internal integer and floating-point execution (or functional) units
• it uses dynamic instruction scheduling and out-of-order execution
• it uses speculative instruction issue (also termed "speculative branching")
• it uses a precise exception model (exceptions can be traced back to the instruction that caused them)
• it uses non-blocking caches
• it has separate on-chip 32-Kbyte primary instruction and data caches
• it has individually-optimized secondary cache and System interface ports
• it has an internal controller for the external secondary cache
• it has an internal System interface controller with multiprocessor support

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The R10000 processor is implemented using 0.35-micron CMOS VLSI circuitry on a single 17 mm-by-18 mm chip that contains about